Citrobits’ HyperRAM memory controller was strategically designed with user accessibility as a top priority, leveraging the AXI 4 interface, widely adopted in modern system architectures. This design choice ensures effortless integration into existing systems, aligning with industry standards and simplifying development processes. Additionally, the HyperBus™ controller offers users the flexibility to configure certain parameters through generics, empowering them to tailor the controller’s operation to their specific requirements. The controller is capable of operating at speeds of up to 200MHz, providing a realistic and reliable solution for a diverse range of memory-intensive tasks.


  • Configurable Generics for initial HyperBus™
  •  Configuration:
    • Drive Strength
    • CS Timming
  • Read Write operations through AXI4-MM:
    • AXI4 clock must be greater or equal to half the HyperBus™ clock frequency
  • AXI4-MM interface 32b, 64b:
    • 128b planned for future releases
  • No delay configuration needed for operation frequency of 10-50 MHz:
  • 200MHz HyperBus™ support:
    • Configurable IODELAY for optimum sampling point (up to 3.2 ns delay)


Hyperbus Memory Controller IP, Block Design, Propel, Radiant

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Hyperbus Controller block diagram

Block Diagram

The block diagram illustrates the connections between the different IP blocks. First, the AXI slave controller will parse the user request. The information will flow to the HyperBus™ controllers by means of two FIFOs that act as frame buffers in case of congestion. The HyperBus™ controller contains the required logic to perform the operations over the memory. There are two FIFOs to perform the clock domain crossing between AXI and HyperBus™.

In HyperBus™ clock domain, there is the data recovery unit, which synchronizes the received data from the physical pins. Finally, the io buffers, that instantiate the buffers and the required delays to the signals


HyperRAM™ memory finds several common uses in video processing applications due to its high-speed data access capabilities and low power consumption. Firstly, it’s frequently employed as a buffer memory for real-time video encoding and decoding tasks, allowing for smooth and uninterrupted data flow between the processor and storage devices. Secondly, HyperRAM™ memory is utilized for frame buffering in video rendering and playback, ensuring seamless playback without dropped frames or glitches. Additionally, it serves as cache memory for frequently accessed video data, improving overall system performance and reducing latency.

Moreover, HyperRAM™ is often integrated into video processing units for temporary storage of intermediate results during image processing operations like filtering, scaling, and color correction, facilitating faster processing and enhancing efficiency. Lastly, HyperRAM™ memory is instrumental in supporting advanced video processing features such as high-definition video streaming, multi-channel video recording, and augmented reality applications, where rapid data access and transfer speeds are critical for a smooth user experience.


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