    250319084906
    #Start recording tcl command: 3/19/2025 08:47:25
    sbp_design open -name system -path {/home/pablo-leyva/Projects/hyperbus-verilog/sources/bd/system/system/system.sbx}
    sbp_config_ip -vlnv {citrobits.com:ip:hyperram:2.0.1} -meta_vlnv {citrobits.com:ip:hyperbus_controller:2.0.1} -cfg_value {CALIBRATION_MODE:1,CS_MAX_LOW_TIME_US:20}
    sbp_replace -vlnv {citrobits.com:ip:hyperram:2.0.1} -name {hyperram_inst} -component {system/hyperram_inst}
    sbp_config_ip -vlnv {latticesemi.com:ip:sysmem:2.3.0} -meta_vlnv {latticesemi.com:ip:system_memory:2.3.0} -cfg_value {ADDR_DEPTH:32768,INIT_MEM:false,INTERFACE:AHBL,PORT_COUNT:2,REGMODE_S0:true}
    sbp_replace -vlnv {latticesemi.com:ip:sysmem:2.3.0} -name {sysmem_inst} -component {system/sysmem_inst}
    sbp_config_ip -vlnv {latticesemi.com:ip:apb_gpio:1.7.0} -meta_vlnv {latticesemi.com:ip:gpio:1.7.0} -cfg_value {EXTERNAL_BUF:true,IO_LINES_COUNT:2}
    sbp_replace -vlnv {latticesemi.com:ip:apb_gpio:1.7.0} -name {apb_gpio_inst} -component {system/apb_gpio_inst}
    sbp_config_ip -vlnv {latticesemi.com:ip:ahbl2axi4_d:1.2.0} -meta_vlnv {latticesemi.com:ip:ahbl2axi4:1.2.0} -cfg_value {NARROW_TRANSFER:true}
    sbp_replace -vlnv {latticesemi.com:ip:ahbl2axi4_d:1.2.0} -name {ahbl2axi4_d_inst} -component {system/ahbl2axi4_d_inst}
    sbp_config_ip -vlnv {latticesemi.com:module:ahbl2apb:1.1.2} -meta_vlnv {latticesemi.com:module:ahb_lite_to_apb_bridge:1.1.2}
    sbp_replace -vlnv {latticesemi.com:module:ahbl2apb:1.1.2} -name {ahbl2apb_inst} -component {system/ahbl2apb_inst}
    sbp_config_ip -vlnv {latticesemi.com:module:ahbl_ic:1.3.2} -meta_vlnv {latticesemi.com:module:ahb_lite_interconnect:1.3.2} -cfg_value {TOTAL_MASTER_CNT:1,TOTAL_SLAVE_CNT:3}
    sbp_replace -vlnv {latticesemi.com:module:ahbl_ic:1.3.2} -name {ahbl_ic_inst} -component {system/ahbl_ic_inst}
    sbp_config_ip -vlnv {latticesemi.com:ip:riscv_proc:2.7.0} -meta_vlnv {latticesemi.com:ip:riscv_mc:2.7.0} -cfg_value {M_STANDALONE:false}
    sbp_replace -vlnv {latticesemi.com:ip:riscv_proc:2.7.0} -name {riscv_proc_inst} -component {system/riscv_proc_inst}
    sbp_design auto_assign_addresses
    sbp_design drc
    sbp_design generate
    sbp_design save
    sbp_design pge sge  -i {/home/pablo-leyva/Projects/hyperbus-verilog/sources/bd/system/system/system.sbx} -o {/home/pablo-leyva/Projects/hyperbus-verilog/sources/bd/system/system/../} -nc
    sbp_design save
    sbp_design generate
    sbp_design pge sge  -i {/home/pablo-leyva/Projects/hyperbus-verilog/sources/bd/system/system/system.sbx} -o {/home/pablo-leyva/Projects/hyperbus-verilog/sources/bd/system/system/../} -nc
    sbp_design close
    #Stop recording: 3/19/2025 08:49:06